1. Technical Field
The present invention relates to a logic circuit simulation apparatus and a logic verification method for use with a logic circuit. More particularly, the invention relates to a simulation apparatus and a logic verification method for use in designing a semiconductor integrated circuit.
2. Background Art
In developing semiconductor integrated circuits, the logic of target circuits are commonly checked before they are manufactured as semiconductor chips. One problem with such procedures is that as semiconductor integrated circuits grow in scale, it takes longer to verify their logic in the design stage. A cycle-based simulator capable of high-speed logic function verification has been attracting attention as a viable way to reduce the time required for logic verification. The cycle-based simulator is a simulator that runs without regard to signal delays on the assumption that every data transfer between registers is carried out in one clock cycle, thereby attaining rapid logic verification. A typical cycle-based simulator may be constructed on a program by a computer system. However, conventional cycle-based simulators are limited in the scope of applicable circuits. These simulators cannot be applied to circuits wherein multi-cycle paths exist, as will be discussed below.
In the cycle-based simulator, a block is extracted for each external connection output terminal and a register arrangement such that a combinational circuit is interposed for data transfer between every external connection input terminal and a register, between one register and another, between every external connection input terminal and every external connection output terminal, and between every external connection output terminal and a register. A combinational circuit is a circuit whose output is uniquely determined with respect to a combination of inputs. Combinational circuits are made of logic gates and selectors with no registers. A block is defined as a combination of a combinational circuit, an external connection input terminal(s) and/or a register(s) connected on the input side to that combinational circuit, and an external connection output terminal and/or a register connected on the output side to the circuit.
FIG. 1 is a partial schematic view of a circuit in which a block is extracted for each external connection output terminal and a register arrangement such that a combinational circuit is interposed for data transfer between every external connection input terminal and a register, between one register and another, between every external connection input terminal and every external connection output terminal, and between every external connection output terminal and a register. In FIG. 1, a circle represents a combinational circuit, a rectangle denotes a register, and a triangle indicates an external connection terminal. Every extracted block belongs to one of typical blocks shown in FIGS. 2 through 7.
FIG. 2 shows a block B1 extracted from the circuit of FIG. 1, wherein data from any external connection input terminal and from a register is transferred to a register REG2 solely through a combinational circuit CL1. In FIG. 2, the combinational circuit CL1 in the block B1 admits data from external connection input terminals IN1 and IN2, as well as an output from the register REG1, and forwards the circuit output as an input to the register REG2.
FIG. 3 shows a block B2 extracted from the circuit of FIG. 1, wherein data from at least one external connection input terminal is transferred to a register REG3 through combinational circuit CL2. In FIG. 3, the combinational circuit CL2 in the block B2 admits data from external connection input terminals IN3, IN4 and IN5, and forwards the circuit output as an input to the register REG3.
FIG. 4 shows a block B3 extracted from the circuit of FIG. 1, wherein data from at least one register is transferred to a register REG7 solely through a combinational circuit CL3. In FIG. 4, the combinational circuit CL3 in the block B3 receives data from registers REG4, REG5 and REG6, and forwards the circuit output as an input to the register REG7.
FIG. 5 shows a block B4 extracted from the circuit of FIG. 1, wherein data from any external connection input terminal and from registers is transferred to an external connection output terminal OUT1 through combinational circuit CL4. In FIG. 5, the combinational circuit CL4 in the block B4 admits data from an external connection input terminal IN5 and from registers REG8, REG9 and REG10, and forwards the circuit output to the external connection output terminal OUT1.
FIG. 6 shows a block B5 extracted from the circuit of FIG. 1, wherein data from any external connection input terminals is transferred to an external connection output terminal OUT2 through combinational circuit CL5. In FIG. 6, the combinational circuit CL5 in the block B5 admits data from external connection input terminals IN3, IN4 and IN6, and forwards the circuit output to the external connection output terminal OUT2.
FIG. 7 shows a block B6 extracted from the circuit of FIG. 1, wherein data from any registers is transferred to an external connection output terminal OUT3 through combinational circuit CL6. In FIG. 7, the combinational circuit CL6 admits data from registers REG8, REG11 and REG12, and forwards the circuit output to the external connection output terminal OUT3.
The cycle-based simulator simulates the circuits extracted as outlined above. With the simulator in operation, the data output of the combinational circuit in each block, and the outputs of registers connected to that circuit on its input side, are transferred without regard to signal delays to implement high-speed logic function verification. Hence, conventional cycle-based simulators are incapable of effecting accurate logic function verification if the output of the combinational circuit in each extracted block, and the outputs of registers connected to that circuit on its input side, are not guaranteed to be output within a delay of one clock cycle from the data input.
FIGS. 8 and 9 illustrate a circuit that may be simulated by a conventional cycle-based simulator under the constraint of one clock cycle delay. FIG. 8 shows, in terms of waveforms with respect to a clock signal, those outputs of the external connection input terminals IN1 and IN2 which are input to the combinational circuit CL1 in the block B1 in FIG. 2, the output of the register REG1 which is also input to the combinational circuit CL1, and the output of the combinational circuit CL1. FIG. 9 is a waveform chart that applies when the same signals shown in FIG. 8 are handled by a cycle-based simulator.
In FIG. 8, reference numeral T1 stands for the time duration of one clock cycle, T2 for a delay from the time the clock cycle is started until data is input from the external connection input terminal IN1, T3 for a delay from the time the clock cycle is started until data is input from the external connection input terminal IN2, and T4 for an output delay of the register REG1 following the clock input.
It takes another delay T5 for the output of the combinational circuit CL1 to be determined following the receipt of the inputs from the external connection input terminals IN1 and IN2, as well as of the output of the register REG1. Thus, the output delay for the combinational circuit CL1 in the first clock cycle is defined as T4+T5. The total delay from the time a clock cycle is changed until the output of the combinational circuit is determined is referred to as the output delay of the combinational circuit.
Further in FIG. 8, reference numeral T6 stands for the output delay of the combinational circuit CL1 in a second clock cycle, T7 for the output delay of the combinational circuit CL1 in a third clock cycle, and T8 for the output delay of the combinational circuit CL1 in a fourth clock cycle. In each of the clock cycles, the output delay of the combinational circuit CL1 does not exceed one clock cycle T1. This makes it possible to acquire the output results shown in FIG. 9, the same as those in FIG. 8, through the use of the conventional cycle-based simulator. In FIG. 9, all signals except a clock signal are changed in the middle of each clock cycle. This is to show that the cycle-based simulator is to change each signal in each clock cycle without regard to delays.
FIGS. 10 through 13 illustrate circuits to which conventional cycle-based simulators cannot be applied. FIGS. 10 and 12 show, in terms of waveforms with respect to the clock signal, those outputs of the external connection input terminals IN1 and IN2 which are input to the combinational circuit CL1 in the block B1 in FIG. 2, the output of the register REG1 which is also input to the combinational circuit CL1, and the output of the combinational circuit CL1. The internal structure of the combinational circuit CL1 and its workings are different from the setups of FIGS. 10 and 12. FIG. 11 represents a case in which the same signals shown in FIG. 10 are handled by a cycle-based simulator. FIG. 13 applies to a case wherein the same signals shown in FIG. 12 are handled by a cycle-based simulator.
In FIG. 10, reference numeral T9 stands for the output delay of the combinational circuit CL1 in the first clock cycle, and T10 for the output delay of the combinational circuit CL1 in the third clock cycle. That is, two clock cycles are required before the circuit output is determined. In such a case, using a conventional cycle-based simulator yields the results in FIG. 11 which differ from those in FIG. 10. This is because neither the first nor the third clock cycle fall within one clock cycle.
In FIG. 12, the output delay of the combinational circuit CL1 in the first clock cycle is T11, requiring one clock cycle before the circuit output is determined. The output delay of the combinational circuit CL1 in the second clock cycle is T12, requiring three clock cycles before the output is determined. In such cases, using a conventional cycle-based simulator yields the results in FIG. 13. While the output result in the first clock cycle that falls within one clock cycle in FIG. 13 is the same as that in FIG. 12, the result in the second clock cycle not effected within one clock cycle differs from that in FIG. 12.
Differences between the results of outputs from the individual blocks are enlarged further for the entire semiconductor integrated circuit. In FIGS. 11 and 13, all signals, except the clock signal, are changed in the middle of each clock cycle. This is to show that the cycle-based simulator is to change each signal in each clock cycle without regard to delays.
As explained with reference to FIGS. 10 and 12, a data transfer route of a combinational circuit that is activated when its output delay exceeds one clock cycle with respect to a combination of inputs is called a multi-cycle path. Circuits comprising such multi-cycle paths cannot be simulated by use of conventional cycle-based simulators.